The amount of memory locations needed to store program instructions and the number of instruction execution cycles required to accomplish a data transfer function in a controller circuit comprising a microprocessor is an important design parameter of a portable electronic device such as a pager, a personal organizer, or a cellular phone. This is because the number of instruction execution cycles relates directly to the amount of time required to complete a function, which directly affects a battery discharge life of such portable electronic device, and because the number of program instructions relates directly to the amount of program memory required for the function, which directly affects the cost of such portable devices.
A function that is commonly used in the microprocessor of such portable devices is a transfer of a set of data words between a microprocessor and a conventional serial communication peripheral device such as a universal asynchronous receiver transmitter (UART) or a serial peripheral interface (SPI). The transfer either transfers the set of data words from the CPU to the serial communication peripheral device for subsequent transmission of the set of data words from the serial communication peripheral device using a bit serial signaling technique, or the transfer transfers the set of data words to the CPU from the serial communication peripheral device that have been received by the serial communication peripheral device using a bit serial signaling technique. In such serial communication peripheral devices a word memory is used to temporarily store the data words that are being serially received or transmitted by the serial communication peripheral device, because the transfer rate used over the serial communications link is typically substantially slower than the transfer rate between the serial communication peripheral device and the CPU. The temporary memory is typically a conventional first in first out (FIFO) register memory that loads and unloads words stored in the well known FIFO manner. The data words stored in the FIFO register are transferred one at a time between the serial communication peripheral device and the CPU through a memory mapped single word register that is within the serial communication peripheral device. The transfer of the data words is typically accomplished by addressing the serial communication peripheral device with one of two predetermined memory mapped addresses each time a data word is transferred: a first address for loading a data word from the serial communication peripheral device into the CPU and a second address for storing a data word into the serial communication peripheral device from the CPU.
Many newer low cost microprocessors, referred to as RISC processors, operate using a reduced instruction set, and typically include not only the single word load instruction and single word store instruction that are invariably provided in any processor, but also include a load multiple instruction and a store multiple instruction. These load and store multiple instructions accomplish a transfer of a entire set of data words using a single program instruction, which is a very efficient technique for transferring a set of data words to a random access memory (RAM). Unfortunately, the load and store multiple instructions are (each) incompatible with a transfer of a set of data words between the CPU and a conventional serial communication peripheral device that uses a data register having a single memory mapped address for a one way transfer of the data words. This incompatibility is due to the fact that the load and store multiple instructions transfer each data word using an associated address that is incremented after each data word in the set of data words.
Thus, what is needed is a technique to transfer a set of data words between a CPU and a serial communication peripheral device when the CPU has the capability to use a load or store multiple instruction and the serial communication peripheral device includes a data register having a single memory mapped register to transfer each data word.